1. Field of Invention
The present invention relates to a method of manufacturing semiconductors. More particularly, the present invention relates to a method of manufacturing a shallow trench isolation alignment mark.
2. Description of Related Art
FIG. 1 is a schematic sketch of a silicon wafer. In FIG. 1, a silicon wafer 2 that includes a first alignment mark 4, a second alignment mark 6 and a main circuit area 8 is provided. The main circuit area 8 includes a number of semiconductor devices (not shown) and integrated circuit regions. The first and the second alignment marks 4 and 6 are positioned near the edge of the wafer 2, and the main circuit area 8 is positioned near the center of the wafer 2. With this arrangement, the first and the second alignment marks 4 and 6 can avoid the central region so that the level of integration in the main circuit region 8 will not be reduced. Furthermore, during the process of fabricating the semiconductor wafer, photomasks must be aligned accurately with respect to the alignment marks 4 and 6 before the main circuit region 8 can be properly formed.
FIGS. 2A through 2F are schematic cross-sectional views taken along line X--X' of FIG. 1 showing the progression of manufacturing steps in producing an alignment mark on a wafer according to a conventional method.
First, as shown in FIG. 2A, a silicon wafer 2 is provided. On the wafer surface 2, an alignment mark 4 having an array profile is formed.
Next, as shown in FIG. 2B, a silicon nitride layer 14 is formed over the wafer 2. Preferably, the silicon nitride layer 14 is formed using a low-pressure chemical vapor deposition (LPCVD) method. Since the silicon nitride layer 14 formed by the LPCVD has good step coverage, an array profile can still be maintained in the silicon nitride layer 14 above the alignment mark 4. Thereafter, shallow trenches (not shown in the FIG.) are formed in the main circuit region 8 of the wafer 2 (FIG. 1). In the conventional method, no shallow trenches are formed around the alignment mark 4 area. The method of forming shallow trenches includes using, for example, photolithographic and dry etching operations. With reference to FIG. 1, note that no shallow trenches are formed on the surface of the wafer 2 outside the main circuit area 8. Consequently, no shallow trenches are found close to the alignment mark 4. Distance of the alignment mark 4 from the main circuit area 8 is roughly more than 2 to 5 times the distance between two neighboring semiconductor devices within the main circuit region 8.
Next, as shown in FIG. 2C, an oxide layer 16 is formed over the silicon nitride layer 14. Preferably, the oxide layer 16 is formed using an atmospheric pressure chemical vapor deposition (APCVD) method. For example, tetra-ethyl-ortho-silicate (TEOS) can be used as a reactive agent for forming the oxide layer 16. In general, the oxide layer 16 has good step coverage, and hence an array profile can be maintained in the oxide layer 16 above the alignment mark 4. Since no shallow trenches are formed near the alignment mark 4, the oxide layer around the alignment mark 4 occupies an area roughly 3 to 6 times the area of oxide layer between two neighboring semiconductor devices in the main circuit area 4.
Next, as shown in FIG. 2D, an oxide chemical-mechanical polishing (Oxide-CMP) operation is performed to remove a portion of the oxide layer 16 above the silicon nitride layer 14. However, it is difficult to remove all oxide material from the surface by using a chemical-mechanical polishing method, especially when the surface of the oxide layer has an array profile or a large surface area. Since the oxide layer 16 has array profile above the alignment mark 4 and the side of the alignment mark 12 is surrounded by large area of oxide material, some residual oxide material 18 will remain over the silicon nitride layer 14 above the array profile after the CMP operation.
Next, as shown in FIG. 2E, the silicon nitride layer 14 is removed using hot phosphoric acid solution, for example.
Finally, as shown in FIG. 2F, traces of the oxide layer 18 are removed using, for example, photolithographic and etching operations with fluorine deficient plasma. In other words, a plasma having a fluorine to carbon (F/C) ratio of less than 4 is used to etch away the oxide material 18 above the alignment mark 4. The process is known as an oxide clearout photo operation.
In the conventional method, the alignment marks is over-shadowed by an array profile and a wide area of surrounding oxide material. Therefore, when an oxide chemical-mechanical polishing operation is carried out, oxide material above the silicon nitride layer close to the alignment mark region is difficult to remove. After the silicon nitride layer is removed, this residual oxide material remains on the alignment mark. The residual oxide material can cause a shift in the overlay structure during subsequent mask alignment operation. Consequently, extra oxide clearout operations may have to be carried out for removing the unwanted oxide material. In light of the foregoing, there is a need for an improved method of forming alignment marks on a silicon wafer.